The present invention relates to electronic circuits, and more particularly, to phase-locked loop circuits.
A phase-locked loop (PLL) is an electronic circuit with an oscillator. A PLL adjusts the frequency of a feedback signal from the output of the oscillator to match in phase the frequency of an input reference clock signal. Phase-locked loops (PLLs) are an essential building block of many integrated circuits, providing periodic signals for data recovery, data transfer, and other clocking functions. PLLs often supply a clock signal to one or more counters or dividers that divide a signal from the oscillator to a lower frequency clock signal for distribution around an integrated circuit or system.
A PLL can be used to stabilize a particular communications channel (i.e., keeping it set to a particular frequency). A PLL can also be used to generate a signal, modulate or demodulate a signal, reconstitute a signal with less noise, or multiply or divide a frequency. PLLs are frequently used in wireless communication, particularly where signals are carried using frequency modulation (FM) or phase modulation (PM). PLLs can also be used in amplitude modulation (AM). PLLs are commonly used for digital data transmission.
The output signal of a voltage controlled oscillator (VCO) in a PLL typically has a valid operating frequency range. If the frequency of the VCO output signal moves outside the valid operating range, the performance of the VCO can degrade substantially. For example, a substantial amount of jitter may be introduced into the VCO output signal. Also, the VCO may stop oscillating or run very fast. Depending on the design margin of other circuitry in the PLL, certain circuit blocks may not be able to keep up with an increased output frequency of the VCO, causing a functional failure in the PLL.
In most applications, designers provide a stable, unchanging input clock signal frequency that stays within an operating range of a PLL. However, some applications allow the frequency of the input clock signal to vary as much as 300%. Therefore, it would be desirable to provide PLLs that can function in response to a wider range of input signal frequencies, while maintaining acceptable phase noise, jitter, and stability performance.